In fabricating highly-integrated memory devices such as dynamic random access memory (DRAM), the area of a memory cell to one stored bit as a basic unit of information has decreased. However, the area of the capacitor should not be decreased in proportion to the memory cell size because capacitance per cell must be higher than a particular fixed value so as to prevent a soft error and maintain stable operation.
Conventionally, it is known that the capacitance of a capacitor can be increased by increasing the capacitor area, by decreasing the effective dielectric thickness, or by using a material with a large dielectric constant. When using a material with a large dielectric constant, a dielectric layer for a capacitor may be made of SiO2. Alternatively, the dielectric layer may have a multi-layered nitride-oxide (hereinafter referred to as “NO”) structure. This NO structure may use SiO2 or Si3N4 with a dielectric constant two times larger than that of SiO2, or oxide-nitride-oxide (hereinafter referred to as “ONO”) structure. However, since each of SiO2, NO, and ONO has a low dielectric constant, decreasing the thickness of the dielectric or increasing the surface area of the dielectric cannot by itself ensure a high capacitance, and, therefore, a new material is required.
To solve this problem, in highly-integrated DRAM, (Ba,Sr)TiO3 (hereinafter referred to as “BST”), (Pb,Zr)TiO3 (hereinafter referred to as “PZT”) and Ta2O5 are used as the material replacing the existing dielectric. Ta2O5 has a dielectric constant (e.g., 20˜25) which is three times larger than the dielectric constant of silicon nitride. Further, Ta2O5 is easily etched compared to BST or PZT. In addition, Ta2O5 has excellent step coverage in chemical vapor deposition (hereinafter referred to as “CVD”). Recently, to improve the unstable stoichiometric ratio of Ta2O5, TaON is being developed.
In a capacitor using Ta2O5 as a dielectric film with a large dielectric constant, the materials used for the electrodes have a marked effect on the characteristics of the dielectric. For example, the dielectric film using Ta2O5 is based on a metal-insulator-silicon (hereinafter referred to as “MIS”) structure instead of the existing NO structure. In “MIS”, “M” means a metal electrode used as a plate node, “I” means a dielectric as an insulator, and “S” means polysilicon used as a storage node. In the Ta2O5 capacitor, a plate electrode used as an upper electrode has a multi-layered structure such as polysilicon/TiN or polysilicon/WN, and a storage electrode used as a bottom electrode is made of polysilicon whose surface is finished by rapid thermal nitration (hereinafter referred as to “RTN”).
Prior art Korean Patent Publication No. 10-2001-0058485 describes a flash memory device having a double nitride layer with a large dielectric constant which is manufactured by depositing an NON film instead of an ONO film to decrease thickness of a gate. U.S. Pat. No. 6,569,731 describes a method of forming an NON structure. The described method comprises the steps of: using silicon nitride deposition to form a SiN layer on a predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitration process with N2O as a reactive gas in a temperature of 800˜1000° C. for 50˜90 minutes to form a nitride layer on the oxide layer.
Conventional methods such as those described above cause problems in process stability because the high-temperature process for forming a single or a multi-layered dielectric has a marked effect on a lower dopant profile. Such conventional methods also cause problems in device reliability because the dopant penetrates into the dielectric layer during a subsequent thermal treatment process. In addition, there are problems such as gate depletion rate reduction and leakage current.